CAN Bit Timing Calculator
Derive prescaler and segment values for a target CAN bitrate.
| Prescaler | Tq/bit | Seg1 | Seg2 | Sample point | Actual rate | Error |
|---|---|---|---|---|---|---|
| 1 | 16 | 13 | 2 | 87.5 % | 500000 | 0.000 % |
| 2 | 8 | 6 | 1 | 87.5 % | 500000 | 0.000 % |
bit = SYNC(1) + SEG1 + SEG2 tq · sample after SEG1 · best row highlighted
This tool derives CAN bit-timing candidates — prescaler, time quanta per bit, SEG1/SEG2 split and resulting sample point — from your controller clock and target bitrate, ranked by bitrate error and closeness to your sample-point target. The classic case: 8 MHz and 500 kbit/s solve exactly with 16 tq and an 87.5 % sample point.
How it works
A CAN bit is assembled from time quanta: one fixed SYNC quantum, then SEG1 (propagation + phase 1) and SEG2 (phase 2). The controller samples the bus between SEG1 and SEG2, so the sample point is (1 + SEG1) / total. The calculator walks every prescaler, keeps totals in the valid 8–25 tq window, splits the segments to approach your sample-point target, and computes the exact bitrate each combination produces — f_clk / (prescaler × total_tq).
Combinations that divide exactly (0 % error) are the ones to use on a shared bus; among them, prefer more quanta per bit for finer phase resolution.
Worked example
prescaler 1 → 16 tq/bit → SEG1 13, SEG2 2
sample point (1+13)/16 = 87.5 % · rate exactly 500 000 bit/s
Parameters
| Parameter | Value | Notes |
|---|---|---|
| Bit composition | SYNC(1) + SEG1 + SEG2 | in time quanta |
| Valid totals | 8 … 25 tq | |
| SEG1 / SEG2 limits | 1–16 / 1–8 tq | |
| Sample point | (1+SEG1)/total | ≈87.5 % conventional |
| Bitrate | f_clk / (prescaler · total) |
C reference
/* CAN bit timing: bit = SYNC(1) + SEG1 + SEG2 time quanta */
/* 8 MHz clock, 500 kbit/s: prescaler 1 -> 16 tq per bit */
/* SEG1 = 13, SEG2 = 2 -> sample point (1+13)/16 = 87.5 % */
uint32_t bit_time_tq = 1 + 13 + 2; /* 16 tq */
uint32_t bitrate = 8000000 / (1 * 16); /* 500000 */
float sample_point = (1 + 13) / 16.0f; /* 0.875 */FAQ
▸What is a time quantum (tq)?
The basic unit the CAN controller divides a bit into: tq = prescaler / f_clk. A bit is built from 1 sync quantum plus SEG1 and SEG2, typically 8–25 tq total. More quanta per bit give finer sample-point placement and better resynchronization.
▸Why does the sample point matter so much?
All nodes on a bus must sample each bit at nearly the same relative position, late enough for the slowest signal to settle across the full cable length. Around 87.5 % is the widely used convention (CANopen recommends it), which is why it is the default target here.
▸Why must the bitrate error be essentially zero for CAN?
Unlike UART, all CAN nodes share one wire and must agree on timing within the resynchronization jitter budget. Practical designs use clock/prescaler combinations that divide exactly — that is why CAN clocks are 8/16/24/48 MHz rather than arbitrary values, and why the table highlights exact-division rows.
▸How do SEG1 and SEG2 map to my controller's registers?
Most controllers (e.g. ST bxCAN, NXP FlexCAN) split SEG1 into PROP_SEG + PHASE_SEG1; this calculator's SEG1 is their sum. Registers usually store 'value − 1', so check whether your header expects the raw quanta count or the register encoding.
▸Is my data uploaded?
No. The search runs locally in your browser.