UART Baud Rate Error Calculator
Actual baud and error % from clock and divider settings.
RISKY — -3.55 % error will likely corrupt frames
| Baud | Divisor | Actual | Error |
|---|---|---|---|
| 9600 | 104 | 9615 | 0.16 % |
| 19200 | 52 | 19231 | 0.16 % |
| 38400 | 26 | 38462 | 0.16 % |
| 57600 | 17 | 58824 | 2.12 % |
| 115200 | 9 | 111111 | -3.55 % |
| 230400 | 4 | 250000 | 8.51 % |
| 460800 | 2 | 500000 | 8.51 % |
| 921600 | 1 | 1000000 | 8.51 % |
This tool computes the integer divisor a UART will actually use for your clock and target baud, the real baud rate that results, and the error percentage — with a PASS/RISKY verdict against the ~±2 % rule of thumb and a table across all common baud rates. The classic trap: 16 MHz at 115200 baud lands 3.55 % slow.
How it works
A UART divides its clock by oversampling × divisor to get the bit clock, and the divisor must be an integer: divisor = round(f_clk / (16 × baud)). Whenever the ideal ratio is not an integer, the rounded divisor shifts the real baud rate. The receiver samples each bit near its center; as clock mismatch accumulates over the ~10 bits of a frame, sampling drifts off the bit cells and bytes corrupt — hence the small tolerance.
The per-baud table makes clock selection obvious at a glance: some clocks are uniformly clean (48 MHz), others degrade precisely at the high rates you care about.
Worked example
divisor = round(8.68) = 9 → actual 111 111 baud
error = −3.55 % (risky) · at 48 MHz: divisor 26 → +0.16 %
Parameters
| Parameter | Value | Notes |
|---|---|---|
| Divisor | round(f_clk/(OS·baud)) | integer |
| Actual baud | f_clk/(OS·divisor) | |
| Oversampling | ×16 (default) or ×8 | |
| Tolerance | ~±2 % per side | rule of thumb |
C reference
/* UART divisor & real baud (16x oversampling) */
uint32_t div_ = (16000000u + 8u * 115200u) / (16u * 115200u); /* round: 9 */
float actual = 16000000.0f / (16u * div_); /* 111111.1 baud */
float err = (actual - 115200) / 115200; /* -3.55 % */
/* 48 MHz instead: divisor 26 -> 115384.6 baud, +0.16 % — clean. */FAQ
▸How much baud error can a UART link tolerate?
A common engineering rule of thumb is to keep each side within about ±2 %, so the combined mismatch stays under ~4–5 % — the point where the last bits of a 10-bit frame sample outside their slots. The verdict banner here uses that ±2 % threshold.
▸Why does 16 MHz give −3.5 % at 115200 baud?
The divisor must be an integer: 16e6/(16×115200) = 8.68, which rounds to 9, producing 111 111 baud — 3.55 % slow. That is exactly why 'weird' crystals like 7.3728 or 11.0592 MHz exist: they divide evenly into all standard baud rates.
▸What does ×8 oversampling change?
Halving the oversampling doubles the available divisor for the same clock, which can land closer to the target at high baud rates — at the cost of noise immunity, since the receiver has fewer samples per bit to vote on.
▸Both my devices show ~3 % error — will the link work?
If both derive from similar clocks and err in the same direction, the relative error is what matters and the link often works. Errors in opposite directions add. Compute both ends here and compare the actual baud values, not the nominal ones.
▸Is my data uploaded?
No. All math runs locally in your browser.