STM32 Timer Calculator
Prescaler/period combinations for a target timer frequency.
| PSC | ARR | Actual (Hz) | Period | Error |
|---|---|---|---|---|
| 1 | 35999 | 1000 | 1.00000 ms | 0.0000 % |
| 2 | 23999 | 1000 | 1.00000 ms | 0.0000 % |
| 3 | 17999 | 1000 | 1.00000 ms | 0.0000 % |
| 4 | 14399 | 1000 | 1.00000 ms | 0.0000 % |
| 5 | 11999 | 1000 | 1.00000 ms | 0.0000 % |
| 7 | 8999 | 1000 | 1.00000 ms | 0.0000 % |
| 8 | 7999 | 1000 | 1.00000 ms | 0.0000 % |
| 9 | 7199 | 1000 | 1.00000 ms | 0.0000 % |
f = f_clk / ((PSC+1) · (ARR+1)) · 16-bit registers · best row highlighted
This tool finds prescaler / auto-reload (PSC/ARR) register pairs that make a 16-bit timer hit a target frequency: f = f_clk / ((PSC+1)·(ARR+1)). It lists the closest pairs ranked by error — exact solutions first — with the resulting period. 72 MHz to 1 kHz solves exactly with PSC 71 / ARR 999, among others.
How it works
A hardware timer divides its input clock twice: the prescaler divides by PSC+1 to produce the counting tick, and the counter overflows after ARR+1 ticks. Hitting a frequency exactly means factoring f_clk / f_target into two integers that both fit in 16 bits. The tool searches that factorization space, including near-miss divisors when no exact split exists, and ranks by relative error with small prescalers preferred — small PSC keeps ARR large, which is what gives PWM its duty-cycle resolution.
Worked example
PSC 71, ARR 999 → 72e6/(72·1000) = 1000.000 Hz (exact)
PWM tip: PSC 0, ARR 71999 → same 1 kHz with 72 000 duty steps
Parameters
| Parameter | Value | Notes |
|---|---|---|
| Formula | f = f_clk/((PSC+1)(ARR+1)) | |
| Register range | 0 … 65535 each | 16-bit timers |
| Period | 1/f | shown per row |
| PWM resolution | ARR+1 steps | prefer small PSC |
C reference
/* Timer update frequency: f = f_clk / ((PSC+1) * (ARR+1)) */
/* 72 MHz -> 1 kHz: 72e6 / 1000 = 72000 = 72 * 1000 */
TIM3->PSC = 72 - 1; /* prescaler: tick = 1 MHz */
TIM3->ARR = 1000 - 1; /* auto-reload: overflow every 1000 */
/* -> update event at exactly 1 kHz, duty resolution 1000 steps */FAQ
▸Why PSC+1 and ARR+1 in the formula?
The registers hold 'divide ratio minus one': a prescaler register of 0 divides by 1, and the counter counts 0…ARR inclusive, which is ARR+1 steps. Forgetting either +1 is the classic reason a timer runs one count fast — the formula is f = f_clk / ((PSC+1)·(ARR+1)).
▸Several exact pairs exist — which should I pick?
For a plain periodic interrupt any exact pair works. For PWM, prefer a small PSC and large ARR: ARR sets the duty resolution (ARR+1 steps), so 72 MHz → 1 kHz with PSC=0/ARR=71999 gives 72000 duty steps versus 1000 with PSC=71/ARR=999.
▸Is this specific to STM32?
The math is generic to any prescaler-plus-autoreload timer (STM32, most ARM MCUs, AVR with its prescaler taps aside). What is STM32-flavored here is the register naming (PSC/ARR) and the 16-bit 0…65535 range; 32-bit timers simply extend the same formula.
▸Why can't some frequencies be hit exactly?
f_clk/f_target must factor into two integers each ≤65536. A 72 MHz clock cannot produce exactly 3 Hz (72e6/3 = 24 000 000 > 65536²·? — the factors exceed the register range), so the tool shows the nearest achievable values with their error instead.
▸Is my data uploaded?
No. The search runs locally in your browser.